VLSI CAD And Signal Integrity Lab
Projects:
“A New Time-Efficient Method for Precise Estimation of Cross-talk Noise on
Multi-line Circuits”
“Evaluation of Existing Test Sets for
Crosstalk Test Coverage using VHDL Hardware Description Language”
The lab is located in the Cherry Engineering Building, second floor room 2632.
Current Tools:
-Hspice
-Prime-time
-Prime-power
-Scirocco VHDL
-Nanosim